Figure 798. Fast Message Dma Read Logic - STMicroelectronics SPC572L series Reference Manual

RM0400
Fast message time stamp register
TIME STAMP [31:0]
Channel 6
Channel 7
Empty
TIME STAMP [31:0]
Received data on a channel (shaded) is stored along with
time stamp and channel number (in white) in the internal buffer

Figure 798. Fast Message DMA read logic

CH
NUM
[3:0]
Fast message CRC register
Channel in sequence will be read
Channel 4
Channel 5
Empty
All channel message registers above are in this format
CH
CRC
NUM
[3:0]
[3:0]
DocID027809 Rev 4
Fast message data register
Status and
Data 1 Data 2
Comm
[3:0] [3:0]
[3:0]
CRC
[3:0]
Reserved bits appended
Channel 2
Channel 3 DMA is
disabled
Status and
Data 1 Data 2
Comm
[3:0] [3:0]
[3:0]
SENT Receiver (SRX)
Data 3 Data 4 Data 5 Data 6
[3:0] [3:0] [3:0]
Channel 1 Channel 0
Data 3 Data 4 Data 5 Data 6
[3:0] [3:0] [3:0]
1399/2058
[3:0]
[3:0]
1410