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RM0400
.
Offset 0x100 + (16*n) + 0x04
0
1
R
W
Reset
0
0
16
17
18
R
W
Reset
0
0
Figure 246. PFlash Calibration Region Descriptor n, Word1 (PFCRDn.Word1)
Table 290. PFlash Overlay Region Descriptor n, Word 1 description
Name
0–27
PSTARTADDR
28.4.1.6.3 PFlash Calibration Region Descriptor n, Word2 (PFCRDn.Word2)
The third word of the calibration region descriptor defines a per-master calibration remap
enable and the remap region size. For cacheable spaces being remapped, the minimum
region size is 32 bytes to match the flash page and cache line sizes. Writes to this word
clear the calibration remap descriptor's valid bit.
.
Offset 0x100 + (16*n) + 0x08
0
1
R
W
Reset
0
0
16
17
18
R
W
Reset
0
0
Figure 247. PFlash Calibration Region Descriptor n, Word2 (PFCRDn.Word2)
2
3
4
5
0
0
0
0
19
20
21
0
0
0
0
Calibration Remap Descriptor n Physical Start Address - This field defines the most
significant bits of the 0-modulo-size physical start byte address of the calibration remap
descriptor. This address corresponds to the physical address which maps to the destination
calibration overlay memory. Any write to PFCRDn.Word{0,1,2} clears the corresponding
PFCRDE[CRDnEN] bit, leaving the calibration remap descriptor invalid.
2
3
4
5
0
0
0
0
19
20
21
0
0
0
0
DocID027809 Rev 4
Flash memory controller (PFLASH Controller)
6
7
8
9
PSTARTADDR
0
0
0
0
22
23
24
25
PSTARTADDR
0
0
0
0
Description
6
7
8
9
0
0
0
0
22
23
24
25
0
0
0
0
Access: Supervisor
10
11
12
13
0
0
0
0
26
27
28
29
0
0
0
0
Access: Supervisor
10
11
12
13
0
0
0
0
26
27
28
29
CRDSize
0
0
0
0
Read/Write
14
15
0
0
30
31
0
0
Read/Write
14
15
0
0
30
31
0
0
577/2058
590
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