Table 387. Icjcmr0–Icjcmr2 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
Offset 0x0B4–0x0BC
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 342. Internal Channel Injected Conversion Mask Registers (ICJCMR0–ICJCMR2)
Field
0–31
JCE_CH[x]
Table 388. Internal Channel Normal Conversion Mask Registers to Channel
Parameter num_intch vector has positional inference for registers ICJCMR0–2, such that:
•
num_intch(i) (i = 0–31) corresponds to ICJCMR0 bit[0:31].
•
num_intch(i) (i = 32–63) corresponds to ICJCMR1 bit[0:31].
•
num_intch(i) (i = 64–95) corresponds to ICJCMR2 bit[0:31].
If any of the num_intch(i) value is '0' corresponding bit is not implemented and read access
returns '0' on that bit location. Thus:
•
If num_intch[31:0] is all 0's, register ICJCMR0 is not implemented
•
If num_intch[63:32] is all 0's, register ICJCMR1 is not implemented
•
if num_intch[95:64] is all 0's, register ICJCMR2 is not implemented.
In any or all of the above circumstances, the corresponding registers are treated as
reserved space and any attempt to access this space generates a transfer error.
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
Table 387. ICJCMR0–ICJCMR2 field descriptions
Injected conversion enable for channel x
0 Injected conversion is disabled for CH[x].
1 Injected conversion is enabled for CH[x].
Register
ICJCMR0
ICJCMR1
ICJCMR2
DocID027809 Rev 4
6 7 8 9
JCE_CH[x]
0 0 0 0
22 23 24 25
JCE_CH[x]
0 0 0 0
Description
Association
Access: User Read/Write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Register bits 31:0
JCE_CH[31:0]
JCE_CH[63:32]
JCE_CH[95:64]
14 15
0 0
30 31
0 0
783/2058
803