Initialization Sequence - STMicroelectronics SPC572L series Reference Manual

RM0400
bit in the first BD for the frame. The driver must follow that with a write to TDAR that triggers
the FEC to poll the next BD in the ring.
48.5.4

Initialization sequence

This section describes which registers are reset due to hardware reset, which registers are
reset by the FEC RISC, and what locations you must initialize prior to enabling the FEC.
48.5.4.1 Hardware Controlled Initialization
In the FEC, hardware resets registers and control logic that generate interrupts. A hardware
reset negates output signals and resets general configuration bits.
Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a
hard reset or software to halt operation). By clearing ECR[ETHER_EN], configuration
control registers such as the TCR and RCR are not reset, but the entire data path is reset.
Register/Machine
XMIT block
RECV block
DMA block
RDAR
TDAR
Descriptor Controller block
48.5.5 User initialization (Prior to Setting ECR[ETHER_EN])
You need to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact
values depend on the particular application. The sequence is not important.
Table 783. ECR[ETHER_EN] De-Assertion Effect on FEC
DocID027809 Rev 4
Fast Ethernet Controller (FEC)
Reset Value
Transmission is aborted (bad CRC appended)
Receive activity is aborted
All DMA activity is terminated
Cleared
Cleared
Halt operation
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