Table 159. Intc_Sscirn Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Figure 111
structure.
Offset: 040h
0
R 0
W
Reset 0
Figure 111. INTC Software Set/Clear Interrupt Registers (INTC_SSCIRn)
Field
Set flag bits. Writing a 1 will set the corresponding CLR bit. Writing a 0 will have no effect.
SET
Each SET is read as a 0.
Clear flag bits. CLR is the flag bit. Writing a 1 to CLR will clear it provided that a 1 is not written
simultaneously to its corresponding SET bit. Writing a 0 to CLR will have no effect.
CLR
0 Interrupt request not pending within INTC.
1 Interrupt request pending within INTC.
18.5.2.6 INTC Priority Select Registers (INTC_PSR0 – INTC_PSR1023)
The Priority Select Registers support the selection of an individual priority for each source of
interrupt request, and the routing of the request to one or more processors. The unique
vector of each peripheral or software-settable interrupt request determines which
INTC_PSRn is assigned to that interrupt request. The software-settable interrupt requests
are assigned the lowest numbered vectors, and their priorities are configured in the lowest
numbered INTC_PSR registers. The peripheral interrupt requests are assigned to vectors
immediately following the software-settable interrupt requests, and their priorities are
configured in the immediately following INTC_PSR registers. The peripheral interrupt
requests are assigned vectors 32–1023, and their priorities are configured in INTC_PSR32–
1023, respectively.
Figure 112
PSRs, respectively. The other registers follow the same numbering scheme.
Note: Unlike the peripheral interrupt request PSRs, there is no SWT bit in the PSRs corresponding
to the software-settable interrupt requests.
Note: Interrupts are not detected while the PSRs are being written.
Offset: 060h
0 1
R
PRC_SEL0
W
Reset 1 0
shows the structure of the first INTC_SSCIR. The other registers follow the same
1 2
0 0
0 0

Table 159. INTC_SSCIRn field descriptions

and Figure 113 show the structure and numbering scheme of the first and last
2 3 4 5
0 0
0 0 0 0
Figure 112. INTC Priority Select Register 0 (INTC_PSR0)
DocID027809 Rev 4
3 4
0 0
0 0
Description
6 7 8 9
0 0 0 0
0 0 0 0
Interrupt Controller (INTC)
Access: User read/write
5 6
0 0
0 0
Access: User read/write
10 11 12 13
PRI0
0 0 0 0
7
CLR
w1c
0
14 15
0 0
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