STMicroelectronics SPC572L series Reference Manual page 166

Device configuration
Field
Disable Receive FIFO
When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-
19
buffered SPI. This bit can only be written when the MDIS bit is cleared.
DIS_RXF
0 Rx FIFO is enabled.
1 Rx FIFO is disabled.
Clear TX FIFO
Flushes the TX FIFO and the CMD FIFO. Writing a '1' to CLR_TXF clears the TX FIFO and CMD
20
FIFO Counters. The CLR_TXF bit is always read as zero.
CLR_TXF
0 Do not clear the Tx FIFO and CMD FIFO counters.
1 Clears the Tx FIFO and CMD FIFO counters.
Flushes the RX FIFO. Writing a '1' to CLR_RXF clears the RX Counter. The CLR_RXF bit is
21 always read as zero.
CLR_RXF 0 Do not clear the Rx FIFO counter.
1 Clear the Rx FIFO counter.
Sample Point
Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid only
when CPHA bit in CTAR is 0.
22–23
00 0 protocol clocks between SCK edge and SIN sample
SMPL_PT
01 1 protocol clock between SCK edge and SIN sample
10 2 protocol clocks between SCK edge and SIN sample
11 Reserved
24–27
This read-only bitfield is reserved and always has the value zero.
Reserved
Extended SPI Mode
This bit enables usage of CTARE (Command and Transfer Attribute Register Extended)
Registers.
CTARE registers allow the user to send up to 32-bit SPI frames. Command Cycling is also enabled
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which allows the user to send mutiple Data Frames using a single Command Frame.
XSPI When MCR[DIS_TXF] is asserted, the Extended SPI Mode cannot be used to transmit SPI frames
which are more than 16 bits in size.
0 Normal SPI Mode. Frame size can be up to 16 bits. Command Cycling is not available in this
mode.
1 Extended SPI Mode. Up to 32-bit SPI Frames along with Command Cycling Enabled
Fast Continuous PCS Mode.
This bit enables the masking of "After SCK (t
operating in Continuous PCS mode. This masking is not available if Continuous SCK mode is
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enabled. The individual delay masks are selected via bits MASC and MCSC of the PUSHR. The
FCPCS
firmware should select appropriate masks when providing continuous frames via the PUSHR.
0 Normal or Slow Continuous PCS mode. Masking of delays is disabled.
1 Fast Continuous PCS mode. Delays masked via control bits in PUSHR.
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Table 47. DSPIx_MCR field descriptions(Continued)
DocID027809 Rev 4
Description
)" and "PCS to SCK (t
ASC
RM0400
)" delays when
CSC