Resets - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
47.9

Resets

The various blocks in LFAST are reset as described in
Table 692. Recommended receive exception handling mechanism
Reset
Asynchronous Hardware reset
DRFRST bit of Mode Configuration
Register (MCR)
DRFEN bit of Mode Configuration
Register (MCR)
47.10 Clocks
The LFAST mainly works on two clocks:
•
System Bus Clock, used to program the registers.
•
System Side Module clock, which is synchronous to the System Bus clock.
47.10.1 Clocking strategy
Figure 682
generate four phases of slow speed clock using both the edges of lfast_sysclk, muxes high
speed and low speed clocks and provides a muxed clock to the Sampler Module.
1286/2058
Polarity: Active Low
– Clock control module (CCM)
– LFAST Domain Logic (Rx and Tx block)
– System Side Module Interface FIFOs
– LFAST Register Space
Polarity: Active High
– Clock control module (CCM)
– LFAST Domain Logic (Rx and Tx block)
– System Side Module Interface FIFOs
– LFAST Register Space
Polarity: Active Low
– Clock control module (CCM)
– LFAST Domain Logic (Rx and Tx block)
– System Side Module Interface FIFOs
– LFAST Status Registers
– SCR[RDR] and SCR[TDR]
– TMCR[CLKTST] and TMCR[LPON]
– ICR[ICLCSEQ] and ICR[SNDICLC]
– PICR[PNGREQ]
– UNSTCR[USNDRQ]
shows the clock domain in which each module functions. The Clock Module will
DocID027809 Rev 4
Table 692.
Blocks Reset