Serial Peripheral Interface (Spi) Configuration - STMicroelectronics SPC572L series Reference Manual

RM0400
46.5.2

Serial Peripheral Interface (SPI) configuration

The SPI configuration transfers data serially using a shift register and a selection of
programmable transfer attributes. The SPI frames can be 32 bits long.
The DSPI is in SPI Configuration when the DCONF field in the MCR is 0b00.
The host CPU or a DMA controller transfers the SPI data from memory external to DSPI
RAM queues to a transmit FIFO (TX FIFO) buffer.
Received data is stored in entries in the Receive FIFO (RX FIFO) buffer. The host CPU or
the DMA controller transfers the received data from the RX FIFO to memory external to the
DSPI.
The FIFO buffers operation is described in
FIFO) buffering
buffering mechanism
Mechanism. The interrupt and DMA request conditions are described in
Interrupts/DMA
The SPI Configuration supports two block-specific modes:
•
Master mode: the DSPI initiates and controls the transfer according to the fields of the
executing CMD FIFO entry.
•
Slave mode: the DSPI only responds to transfers initiated by a bus master external to
the DSPI and the SPI command field space is reserved.
46.5.2.1 Master mode
In SPI Master mode, the DSPI initiates the serial transfers by controlling the Serial
Communications Clock (SCK) and the Peripheral Chip Select (PCS) signals.
The executing SPI CMD FIFO entry determines which CTARs will be used to set the transfer
attributes and which PCS signals to assert. The command field also contains various bits
that help with queue management and transfer protocol. See DSPI PUSH FIFO Register
(PUSHR) for details on the SPI command fields.
The data in the executing TX FIFO entry is loaded into the shift register and shifted out on
the Serial Out (SOUT) pin.
In SPI Master mode, each SPI frame to be transmitted has a command associated with it for
transfer attribute control on a frame-by-frame basis.
In Extended SPI Master mode, multiple SPI frames can have a single command associated
with them allowing for efficient SPI frame transfers requiring common transfer attributes.
Extended SPI Mode allows for larger frame sizes of up to 32 bits.
46.5.2.2 Slave mode
In SPI slave mode, the DSPI responds to transfers initiated by a SPI bus master. The DSPI
does not initiate transfers.
Certain transfer attributes such as clock polarity, clock phase and frame size must be set in
CTAR0 and CTARE0 for successful communication with an SPI master. The data is shifted
out with MSB first; shifting out of LSB is not supported in this mode.
mechanism, Section 46.5.2.5: Command First In First Out (CMD FIFO)
and Section 46.5.2.6: Receive First In First Out (RX FIFO) Buffering
requests.
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
Section 46.5.2.4: Transmit First In First Out (TX
Section 46.5.12:
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