Embedded memories
3
Embedded memories
3.1
Overview
The embedded memory architecture for SPC572Lx devices is a significant departure from
previous-generation devices. Features include:
•
Onboard system SRAM and overlay SRAM
•
Onboard system error correction code (ECC) flash memory
•
Embedded memories in the peripherals
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3.2
SRAM
3.2.1
System SRAM
SPC572Lx devices include 64 KB of general-purpose on-chip ECC SRAM. The SRAM can
be configured for either zero- or one-wait state read operation latency using the PRCR1
register in the SRAM controller.
•
See
controller.
•
See
map.
3.2.2
Overlay SRAM
Overlay SRAM is included in the SPC572Lx family of devices as part of a comprehensive
set of calibration and debug features. Overlay SRAM can be mapped over specific regions
of on-chip flash memory so that any access to an overlaid flash address is routed to the
overlay SRAM instead. This enables the calibration of constant data without requiring
additional external RAMs and calibration memory interfaces.The SPC572Lx has two 4 KB
banks of ECC-protected RAM, for a total of 8 KB.
Note:
Overlay SRAM is normally used for system development purposes only. Code can be
executed from internal overlay RAM and extended overlay RAM where available. Execution
from overlay RAM remapped over Flash can be enabled or disabled by use of
PFCRCR[IRMEM]. Code can be executed directly from internal Overlay RAM (address
range beginning 0x0D000000) regardless of the PFCRCR[IRMEM] setting.
Overlay memory can be used to hold the device debug trace stream. Timing for calibration
accesses to a particular overlay SRAM is the same as access to the underlying flash
memory if the overlay SRAM is not being used as a destination for trace streaming at the
same time.
a. Refer to the respective module chapter for details.
100/2058
CAN
eDMA
FEC
GTM
Chapter 27: RAM controller (PRAM)
Table 10: RAM memory map
DocID027809 Rev 4
(a)
:
for details on configuring the SRAM
in
Chapter 5: Memory map
RM0400
for the SPC572Lx SRAM
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