Table 647. Peripheral Chip Select Strobe Assert Computation Example - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
The delay between the assertion of the PCS signals and the assertion of PCSS is selected
by the PCSSCK field in the CTAR based on the following formula:
Equation 23
At the end of the transfer the delay between PCSS negation and PCS negation is selected
by the PASC field in the CTAR based on the following formula:
Equation 24
Table 647

Table 647. Peripheral Chip Select Strobe Assert Computation Example

100 MHz
Table 648
Table 648. Peripheral Chip Select Strobe Negate Computation Example
100 MHz
The PCSS signal is not supported when Continuous Serial Communication SCK or TSB
mode are enabled.
Note: The clock frequency mentioned in the preceding
example. Refer to the clocking chapter for the frequency used to drive this module in the
device.
1192/2058
Figure 618. Peripheral Chip Select Strobe Timing
shows an example of how to compute the t
f PCSSCK
P
shows an example of how to compute the t
f PASC
P
DocID027809 Rev 4
1
---- - ×
t = PCSSCK
PCSSCK
f
P
1
---- - ×
t = PASC
PASC
f
P
PCSSCK
Prescaler
0b11
PASC
Prescaler
0b11
Table 647
delay.
Delay before transfer
7 70.0 ns
delay.
Delay after transfer
7 70.0 ns
and Table 648 is given as an
RM0400