Table 964. Dci Operating Modes - STMicroelectronics SPC572L series Reference Manual

RM0400
Mode
DCI_JTAG
DCI_SW_DBG
58.1.3.1 Software enabled debug and calibration mode
Apart from the JTAG sources, such as a JTAG-based tool , it is possible to generate JTAG
sequences through software programming using JTAGM IP.
To support a software debug session via a CAN or SPI link, the software can enable debug
and calibration mode via an memory-mapped register. It is done first by setting a control bit
in the JTAGM (JTAGM_MCR[DTM]). For more details, refer to the JTAGM documentation.
When enabled, the DCI is configured to receive M.JTAG signals which are driven by JTAGM
registers accessible through software. Software can control all DCI features like any other
JTAG source.
After a system reset, the JTAGM_MCR[DTM] bit is reset and the JCOMP pad is pulled-low,
thus keeping the DCI in the reset state. Therefore, software is required to first change to a
non-secured mode. Then it can program the JTAGM_MCR[DTM] bit, to select M.JTAG as
the source inside the DCI, and then set the JTAGM_MCR[jtagm_JCOMP] bit present in the
JTAGM, which takes all debug modules out of reset.
There is a software programmable bit, MCR[jtagm_JCOMP], present in JTAGM block which,
when programmed to 0, asserts reset for the JTAGC block, thus putting the debug and
calibration logic in reset state. This bit is used during software based debug to initialize the
debug and calibration logic.
Software based debug is not possible when a tool is connected. The presence of the tool is
determined using the rising edge of the JCOMP pad to set an internal flag which, when set,
disables the selection of JTAGM as a JTAG source.
Note: It is recommended to utilize either hardware based debug (JTAG ) or software based debug.
If only one of the debug method is used, all three connection methods (connect and reset
target, connect and break application, connect and keep application running) are supported.
Note: If both debug methods are used simultaneously, then an external tool may arbitrarily
connect when the SoC has already been halted using the software debug mode. In this
case, two consecutive assertions of external JCOMP are necessary to allow the external
tool to take control of debug session.
58.1.3.2 Nexus reset control
The JCOMP input that is used as the primary reset signal for the DCI is also used by the
DCI to generate a single-bit reset signal for other Nexus blocks. It is used to reset all debug

Table 964. DCI operating modes

JTAG mode. This is the default state after power-on reset. In this mode the DCI is in
JTAG mode (controlled with P.JTAG) and is controlled by an external JTAG tool.
Software Debug State. This state is achieved when no tool is present and software sets
the JTAGM_MCR[DTM] bit. The DCI is then controlled using M.JTAG signals.
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Debug and Calibration Interface (DCI)
Description
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