Processor Core Local Sram; Embedded Flash Memory - STMicroelectronics SPC572L series Reference Manual

RM0400
The calibration remap function supports two different types of overlay SRAM:
•
An internal overlay RAM is included on all standard production devices.
•
A portion of the system RAM can be used as the overlay RAM.
The overlay function is implemented using registers in the flash memory controller.
1. Using PFlash Calibration Region Descriptors (PFCRDn) define one or more (up to 32)
overlay regions.
2. Enable individual regions using the appropriate bits in the PFLASH Remap Descriptor
Enable Register (PFDCRDE).
3. Enable overlay using the PFCRCR[GRMEN] field.
See Section 28.5.12: PFlash calibration remap
(remapping).
3.2.3

Processor core local SRAM

SPC572Lx devices include local instruction and data SRAM (I-MEM and D-MEM) for each
processor core to provide enhanced performance.
•
Each main processor core has 16 KB of instruction SRAM and 64 KB of data SRAM.
•
The peripheral processor core has 16 KB of instruction SRAM and KB data SRAM.
The core SRAM supports zero wait-state, single-cycle latency on processor local accesses.
Each area of core SRAM is accessible by other processor cores and bus mastering
peripheral devices. See
3.3

Embedded flash memory

Flash memory on SPC572Lx devices consists of a flash memory controller and a flash
memory array module. The flash controller provides flash configuration and control
functions and manages the interface between the flash memory array and the device
crossbar switch.
Table 10: RAM memory map
Figure 4 shows the memory architecture.
DocID027809 Rev 4
Embedded memories
support, for details on memory overlay
in Chapter 5: Memory map for details.
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