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System Integration Unit Lite2 (SIUL2)
13.2
Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL2 module.
13.2.1
Memory map
Table 112
Address
offset
0x0000
SIUL2 MCU ID Register #1
0x0004
(SIUL2_MIDR1)
SIUL2 MCU ID Register #2
0x0008
(SIUL2_MIDR2)
0x000C–
0x000F
SIUL2 DMA/Interrupt Status Flag Register 0
0x0010
(SIUL2_DISR0)
0x0014–
0x0017
SIUL2 DMA/Interrupt Request Enable Register 0
0x0018
(SIUL2_DIRER0)
0x001C–
0x001F
SIUL2 DMA/Interrupt Request Select Register 0
0x0020
(SIUL2_DIRSR0)
0x0024
SIUL2 Interrupt Rising-Edge Event Enable Register 0
0x0028
(SIUL2_IREER0)
0x002C
SIUL2 Interrupt Falling-Edge Event Enable Register 0
0x0030
(SIUL2_IFEER0)
0x0034
SIUL2 Interrupt Filter Enable Register 0
0x0038
(SIUL2_IFER0)
0x003C
SIUL2 Interrupt Filter Maximum Counter Register 0–
0x0040–
Interrupt Filter Maximum Counter Register 31
0x00BC
(SIUL2_IFMCR0–SIUL2_IFMCR31)
286/2058
gives an overview of the SIUL2 registers implemented.
Table 112. SIUL2 memory map
Register name
DocID027809 Rev 4
Reserved
R
R
Reserved
R/
W
Reserved
R/
W
Reserved
R/
W
Reserved
R/
W
Reserved
R/
W
Reserved
R/
W
Reserved
R/
W
RM0400
Location
32
32
on page 288
32
32
on page 288
32 32/16/8
on page 290
32 32/16/8
on page 291
32 32/16/8
on page 292
32 32/16/8
on page 293
32 32/16/8
on page 294
32 32/16/8
on page 294
32
32
on page 295
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