Table 797. Fdma_Ctrl Field Descriptions - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
Address Offset: 0x0028
0
R
W
Reset 0
8
R
W
Reset 0
16
R FDMA_EN1
FDMA_EN1
5
W
Reset 0
24
R
FDMA_EN7 FDMA_EN6 FDMA_EN5 FDMA_EN4 FDMA_EN3 FDMA_EN2 FDMA_EN1 FDMA_EN0
W
Reset 0
Figure 785. Fast Message DMA Control Register (FDMA_CTRL)
Field
0:15 Reserved. Read returns zero
Enable DMA for Fast Messages on Channels 0 to 15. These bits are writeable when corresponding
Fast Message Ready Interrupt Enable bits are set to 0.
16:31
FDMA_ENn
0 – DMA for Fast Messages is disabled
(n = 15 to 0)
1 – DMA for Fast Messages is enabled
49.3.2.9 Slow Serial Message DMA Control Register (SDMA_CTRL)
Note: The following register figure and table shows the maximum possible configuration but the
exact number of valid register bits are dependent on supported SENT channels on the
device. Please see Device Configuration chapter for number of support SENT channels.
Reads of bits beyond the supported number of channels should be ignored and writes to
these bits are unadvisable and may cause unexpected behavior.
1378/2058
1 2
0 0
9 10
0 0
17 18
FDMA_EN1 FDMA_EN1
4 3
0 0
25 26
0 0

Table 797. FDMA_CTRL field descriptions

DocID027809 Rev 4
3 4
0 0
11 12
0 0
19 20
FDMA_EN1 FDMA_EN1
2 1
0 0
27 28
0 0
Description
Access: RW
5 6
0 0
13 14
0 0
21 22
FDMA_EN9 FDMA_EN8
0
0 0
29 30
0 0
RM0400
7
0
15
0
23
0
31
0