Figure 488. Interrupt Line Enable Register - STMicroelectronics SPC572L series Reference Manual

CAN Subsystem
Table 540. Interrupt line select register field descriptions(Continued)
Field
High Priority Message Interrupt Line
23
0 Interrupt assigned to interrupt line M_CAN INT0
HPML
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 1 Message Lost Interrupt Line
24
0 Interrupt assigned to interrupt line M_CAN INT0
RF1LL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 1 Full Interrupt Line
25
0 Interrupt assigned to interrupt line M_CAN INT0
RF1FL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 1 Watermark Reached Interrupt Line
26
0 Interrupt assigned to interrupt line M_CAN INT0
RF1WL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 1 New Message Interrupt Line
27
0 Interrupt assigned to interrupt line M_CAN INT0
RF1NL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 0 Message Lost Interrupt Line
28
0 Interrupt assigned to interrupt line M_CAN INT0
RF0LL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 0 Full Interrupt Line
29
0 Interrupt assigned to interrupt line M_CAN INT0
RF0FL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 0 Watermark Reached Interrupt Line
30
0 Interrupt assigned to interrupt line M_CAN INT0
RF0WL
1 Interrupt assigned to interrupt line M_CAN INT1
Rx FIFO 0 New Message Interrupt Line
31
0 Interrupt assigned to interrupt line M_CAN INT0
RF0NL
1 Interrupt assigned to interrupt line M_CAN INT1
44.3.5.2.17 Interrupt Line Enable Register (ILE)
Each of the two interrupt lines to the CPU can be enabled / disabled separately by
programming bits EINT0 and EINT1.
Address: 0x005C
0 1 2
R 0 0 0
W
Reset 0 0 0
16 17 18
R 0 0 0
W
Reset 0 0 0
1026/2058
3 4 5 6
0 0 0 0
0 0 0 0
19 20 21 22
0 0 0 0
0 0 0 0

Figure 488. Interrupt line enable register

DocID027809 Rev 4
Description
7 8 9 10
0 0 0 0
0 0 0 0
23 24 25 26
0 0 0 0
0 0 0 0
RM0400
Access: RW
11 12 13 14
0 0 0 0
0 0 0 0
27 28 29 30
0 0 0
0 0 0 0
15
0
0
31
0