STMicroelectronics SPC572L series Reference Manual page 170

Device configuration
Register description
LIN Error Status register (LINESR)
UART Mode Control register (UARTCR)
UART Mode Status register (UARTSR)
LIN Timeout Control Status register (LINTCSR)
LIN Output Compare register (LINOCR)
LIN Timeout Control register (LINTOCR)
LIN Fractional Baud Rate register (LINFBRR)
LIN Integer Baud Rate register (LINIBRR)
LIN Checksum Field register (LINCFR)
LIN Control register 2 (LINCR2)
Buffer Identifier register (BIDR)
Buffer Data Register Least Significant (BDRL)
Buffer Data Register Most Significant (BDRM)
Identifier Filter Enable register (IFER)
Identifier Filter Match index (IFMI)
Identifier Filter Mode register (IFMR)
Identifier Filter Control registers (IFCR0)
Identifier Filter Control registers (IFCR1)
Identifier Filter Control registers (IFCR2)
Identifier Filter Control registers (IFCR3)
Identifier Filter Control registers (IFCR4)
Identifier Filter Control registers (IFCR5)
Identifier Filter Control registers (IFCR6)
Identifier Filter Control registers (IFCR7)
Identifier Filter Control registers (IFCR8)
Identifier Filter Control registers (IFCR9)
Identifier Filter Control registers (IFCR10)
Identifier Filter Control registers (IFCR11)
Identifier Filter Control registers (IFCR12)
Identifier Filter Control registers (IFCR13)
Identifier Filter Control registers (IFCR14)
Identifier Filter Control registers (IFCR15)
Global Control register (GCR)
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Table 50. LINFlexD implemented registers(Continued)
DocID027809 Rev 4
linflex_0
0xFFE8C000
Address offset Address offset
(hex)
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C
50
54
58
5C
60
64
68
6C
70
74
78
7C
80
84
88
8C
linflex_1 linflex_14
0xFFE90000 0xFFEA8000
Address offset
(hex)
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4C
RM0400
(hex)
0C
10
14
18
1C
20
24
28
2C
30
34
38
3C
40
44
48
4C