Dma Read Logic - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
Section 49.3.2.10: Fast Message Ready Interrupt Control Register (FRDY_IE)
Section 49.3.2.9: Slow Serial Message DMA Control Register (SDMA_CTRL)
49.4.2

DMA read logic

The SENT module generates separate DMA requests for all Fast Messages and Slow Serial
Messages received. The DMA requests are common for all channels. Each packet stored in
the channels' buffers are appended with a time stamp taken from a free running time
keeping counter and the channel number on which it was received. Details on this time
stamp counter can be found in
49.4.2.1 DMA request for Fast Message reading
Fast Messages received are stored in a single system bus clock domain buffer to be read
out by the DMA Controller via the DMA Fast Message Read register set. Note the DMA
Controller must read all 3 DMA Read Registers to obtain the complete message. The data
flow will happen as follows:
•
A DMA request will be asserted when any of the DMA enabled channels has
successfully received one complete Fast Message. The request is kept asserted till all
messages (across DMA enabled channels) have been read out.
•
DMA Controller should read the complete message by accessing each register of the
DMA Fast Message Read register set, the registers being:
–
–
–
•
A fixed round robin sequencing runs, as shown in
messages in sequence 0→1→3 →5→7 and back to channel 0 and so on. Channel 2 is
skipped as it's not DMA enabled) and channel 4 and 6 are skipped as message is not
received completely. This sequence continues like this.
• The sequence in which messages are read through DMA interface is not deterministic
and depends on the sequence in which they are completely received.
•
When the sequencing logic detects a message ready to be read, it will update the DMA
Fast Message Read register set for DMA read and move to the next channel when this
message is read out completely (i.e., 3 read accesses to the above mentioned
registers)
•
The DMA controller should be programmed to read only one message in one DMA
transfer (i.e. 12 bytes). If it is programmed to read more than one message in one DMA
transfer, underflow in buffers might occur
•
User software should ensure there is no overflow in channels. In case overflow occurs,
the message in the channel buffer will get overwritten by the newly received message.
However, when a DMA read is in progress, the buffers will not be overwritten if overflow
occurs to maintain data integrity.
•
The Round Robin sequencing logic loops through each DMA enabled channel and
halts at any channel having data till it is read out by the DMA Controller.
1398/2058
Section 49.3.2.12: DMA Fast Message Data Read Register (DMA_FMSG_DATA)
Section 49.3.2.13: DMA Fast Message CRC Read Register (DMA_FMSG_CRC)
Section 49.3.2.14: DMA Fast Message Time Stamp Read Register
(DMA_FMSG_TS)
DocID027809 Rev 4
Section 49.4.8: Time stamp logic on page 1407.
Figure 798, and this logic checks for
RM0400
and