Timer - STMicroelectronics SPC572L series Reference Manual

LINFlexD
When automatic synchronization is enabled, after each LIN Sync Del, the time duration
between five falling edges on RDI is sampled on LIN_CLK.
50.3.2.10 Wakeup management
Any node in a sleeping LIN cluster may request a wakeup. The wakeup request is issued by
forcing the bus to the dominant state for 250 µs to 5 ms. Every slave node should detect the
wakeup request (a dominant pulse longer than 150 µs) and be ready to listen to bus
commands within 100 ms, measured from the ending edge of the dominant pulse. The
master also wakes on detecting a wakeup request and when the slaves are ready, starts
sending frame headers to find out the cause of the wakeup. If the master does not issue a
frame header within 150 ms from the wakeup request, then the node issuing a request may
try issuing a new wakeup request.
In LINFlexD, a wakeup request can be generated by writing the wakeup character in BDR0
and setting the WURQ bit in LINCR2. On setting the WURQ bit, the character in BDR0 is
transmitted. For LIN 2.0, character 0xF0 is sent as the wakeup character.
In LINFlexD, wakeup can be detected in two ways.
1. AUTOWU = 1
On detecting a falling edge in sleep mode, the SLEEP bit is cleared by hardware, the
WUF flag is set, and an interrupt is generated (if WUPIE is set). LINFlexD is now in
normal mode and ready to receive frames.
2. AUTOWU = 0
On detecting a falling edge the WUF flag is set and an interrupt is generated (if WUPIE
is set). It is then up to the software to clear the SLEEP bit.
150 µs
Wakeup pulse
50.3.3

Timer

There is an 8 bit counter which has different behavior in different modes.
In Output Compare Mode (LINTCSR[MODE]= 1) : This counter is running even in Sleep and
Initialization mode. The counter value which when matches the two software configurable
output compare registers (LINOCR[OC1] or LINOCR[OC2]), generate output compare
interrupt (LINESR[OCF]) provided TOCE bit in LINTCSR is set. Once an interrupt occurs
subsequent interrupt is generated only when the application has soft reset the LIN IP
through GCR [SR] bit to get reset the output compare flag (LINESR[OCF]).
In LIN Mode : The software has no control over the TOCE bit and output compare registers
are utilized for generation of LIN timeout interrupts (header, frame, response times out). In
this case, if LIN moves to Sleep or Init state then this counter remains in Reset state. LIN
mode has no meaning if UART is enabled, hence the counter will remain in Reset state.
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Figure 824. Wakeup sequence
100 ms
DocID027809 Rev 4
RM0400
Header
Response