RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
Parameter num_intch vector has positional inference for registers ICWER0–2, such that:
•
num_intch(i) (i = 0–31) corresponds to ICWER0 bit[0:31]
•
num_intch(i) (i = 32–63) corresponds to ICWER1 bit[0:31]
•
num_intch(i) (i = 64–95) corresponds to ICWER2 bit[0:31]
If any num_intch(i) value is '0', the corresponding bit is not implemented and read access
returns '0' on that bit location. Thus:
•
if num_intch[31:0] is all 0's, register ICWER0 is not implemented.
•
if num_intch[63:32] is all 0's, register ICWER1 is not implemented.
•
if num_intch[95:64] is all 0's, register ICWER2 is not implemented.
In any or all of the above circumstances, the corresponding registers are treated as
reserved space and any attempt to access this space generates a transfer error.
36.5.1.20 Internal Channel Analog Watchdog Out of Range Registers 0–2 (ICAWORR0–
ICAWORR2)
The analog watchdog registers to channel association is described in
Offset 0x2F0–0x2F8
0
1
R
W
Reset
0
0
16
17
R
W
Reset
0
0
Figure 348. Internal Channel Analog Watchdog Out of Range Registers (ICAWORR0–ICAWORR2)
Field
0–31
AWOR_CH[x]
Note:
In case either num_watchdog is zero, these registers are not implemented.
Table 397. Internal Channel Analog Watchdog Registers to Channel Association
2
3
4
5
0
0
0
0
18
19
20
21
0
0
0
0
Table 396. ICAWORR0–ICAWORR2 field descriptions
AWOR_CH[x]: Analog watchdog out of range status for channel x
corresponding WEN_CHx bit is set.
0 CH[x] converted data is not out of range determined by its thresholds.
1 CH[x] converted data is out of range determined by its thresholds.
Register
ICAWORR0
ICAWORR1
ICAWORR2
DocID027809 Rev 4
6
7
8
9
AWOR_CH[x]
w1c
0
0
0
0
22
23
24
25
AWOR_CH[x]
w1c
0
0
0
0
Description
Table
397.
Access: User Read Only
10
11
12
13
0
0
0
0
26
27
28
29
0
0
0
0
, provided
Register bits 31:0
AWOR_CH[31:0]
AWOR_CH[63:32]
AWOR_CH[95:64]
14
15
0
0
30
31
0
0
789/2058
803
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