Dma Functionality - STMicroelectronics SPC572L series Reference Manual

RM0400 Successive Approximation Register Analog-to-Digital Converter (SARADC) Digital Inter-
threshold values. Enabling is done by setting the bit corresponding to channel 30 in
ICWENR0 register.
If the converted value for a particular channel lies outside the range specified by threshold
values, then the corresponding bit is set in ICAWORR0–2, TCAWORR, ECAWORR0–3
registers. In this case, a set of threshold registers (THRHLR0–15) can be linked to several
analog channels. The threshold values to be selected for a channel needs be programmed
only once in ICWSELR, TCWSELR, ECWSELR registers.
Note: If the higher threshold for the analog watchdog is programmed lower than the lower
threshold and the converted value is less than the lower threshold, then the WDGxL
interrupt for the low threshold violation is set, else if the converted value is greater than the
lower threshold (consequently also greater than the higher threshold) then the interrupt
WDGxH for high threshold violation is set. The user should therefore take care to avoid this
situation as it could lead to misinterpretation of the watchdog interrupts.
36.4.7

DMA functionality

A Direct Memory Access (DMA) request can be programmed after the conversion of every
channel by setting the respective masking bit in ICDSR0–2, TCDSR and ECDSR0–3
registers. The DMA masking registers must be programmed before starting any conversion.
The DMA transfers can be enabled using the DMAE[DMAEN] bit. When the DMAE[DCLR]
bit is set, the DMA request is cleared on the reading of the register for which DMA transfer
has been enabled.
36.4.8 Interrupts
The SARADC digital interface generates the following maskable interrupt signals:
•
End Of Conversion interrupts
–
–
–
–
The EOC_CH[x] bit of interrupt pending registers (ICIPR0–2, TCIPR) is set when channel x
completes the conversion (normal or injection). This pending status is qualified when the
corresponding mask bit IM_CH[x] is also set in the interrupt mask registers (ICIMR0–2,
TCIMR).
The NEOC interrupt is generated only if the following conditions are met
–
–
–
The JEOC interrupt is generated only if the following conditions are met
–
–
–
It is recommended to clear the NEOC/JEOC/EOCTU bits of ISR and all the individual
channel pending bits which are not masked while servicing the interrupt.
NEOC (end of normal conversion of each channel)
NECH (end of normal chain)
JEOC (end of injected conversion of each channel)
JECH (end of injected chain)
ISR[NEOC] bit is set after the normal conversion completion for any channel x.
IMR[MSKNEOC] bit is set
EOC_CH[x], IM_CH[x] bits are set at least for one channel x
ISR[JEOC] bit is set after the injected conversion completion for any channel x.
IMR[MSKJEOC] bit is set
EOC_CH[x], IM_CH[x] bits are set at least for one channel x
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