Table 529. Test Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
0:14 Reserved
Transceiver Delay Compensation Value
19:23
0x00–0x1F— Position of the secondary sample point, defined by the sum of the measured delay
TDCV
from m_can_tx to m_can_rx and FBTP.TDCO. Valid values are 0 to 31 M_CAN core clock periods.
Receive Pin
24
Monitors the actual value of pin m_ can_rx
RX
0 The CAN bus is dominant (m_can_rx = '0')
1 The CAN bus is recessive (m_can_rx = '1')
Control of Transmit Pin
00 Reset value, m_can_tx is controlled by the CAN core, updated at the end of the CAN bit time
25:26
01 Sample Point can be monitored at pin m_can_tx
TX
10 Dominant ('0') level at pin m_can_tx
11 Recessive ('1') at pin m_ can_tx
Loop Back mode
27
0 Reset value, Loop Back mode is disabled
LBCK
1 Loop Back mode is enabled (see
28:31 Reserved
44.3.5.2.5 RAM Watchdog Register (RWD)
The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM
access via the M_CAN's Generic Master Interface starts the Message RAM Watchdog
Counter with the value configured by the WDC bits. The counter is reloaded with WDC bits
when the Message RAM signals successful completion by activating its READY output. In
case there is no response from the Message RAM until the counter has counted down to
zero, the counter stops and interrupt flag WDI bit of the IR register is set. The RAM
Watchdog Counter is clocked by the Host clock .
Address: 0x0014
0 1
R 0 0
W
Reset 0 0
16 17 18
R
W
Reset 0 0
1. These are protected write (P) bits which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0
[INIT] of CCCR register are set to "1".

Table 529. Test Register field descriptions

2 3 4 5
0 0 0 0
0 0 0 0
19 20 21
WDV
0 0 0 0
Figure 476. RAM watchdog register
Description
Section 44.3.7.8: Test
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
DocID027809 Rev 4
CAN Subsystem
modes)
Access: Read Protected
10 11 12 13
0 0 0
0 0 0
26 27 28 29
(1)
WDC
0 0 0
14 15
0 0 0
0 0 0
30 31
0 0 0
1007/2058
1091