Censorship - STMicroelectronics SPC572L series Reference Manual

RM0400
28.5.7

Censorship

The entire flash space is defined by three major regions:
•
Code flash (instruction and constant data)
•
Data flash (data for EEPROM emulation)
•
TEST flash
Each section can be independently censored, and the flash memory controller provides
independent censorship control inputs for each region on a read vs. write basis.
28.5.8 Line read buffers and prefetch operation
The AHB port of the flash memory controller containsa two-way set-associative mini cache,
where each way contains four page buffers which are used to hold data read from the flash
arrays. Each 128-bit buffer operates independently, and is filled using a single array access.
The buffers are used for both prefetch and normal demand fetches.
Prefetch triggering is controllable on a per-master and access-type basis (see
Section 28.4.1.1: Platform Flash Configuration Register 1
enabled or disabled from triggering prefetches, and triggering may be further restricted
based on whether a read access is for instruction or data. A read access by the flash
memory controller may trigger a prefetch to the next sequential line of array data on the
cycle following the request. The access address is incremented by 16-bytes, and a
subsequent flash access is initiated. A flash array prefetch is initiated if the data is not
already resident in a line read buffer. Prefetched data is always loaded into the least-
recently-used buffer.
Figure 248. Flash memory controller 4-entry, 4-way mini-cache organization
Once the candidate line buffer has been selected, the flash array is accessed and read data
loaded into the buffer. If the buffer load was in response to a miss, the just-loaded buffer is
immediately marked as most-recently-used. If the buffer load was in response to a
speculative fetch to the next-sequential line address after a buffer hit, the recently-used
status is not changed. Rather, it is marked as most-recently-used only after a subsequent
buffer hit.
This policy maximizes performance based on reference patterns of flash accesses and
allows for prefetched data to remain valid when non-prefetch enabled bus masters are
granted flash access.
Several algorithms are available for prefetch control which trade off performance for power.
They are described in
More aggressive prefetching may increase power due to the number of potentially discarded
prefetches, but may increase performance by lowering average read latency.
WAY0
set0
set1
set2
set3
Section 28.4.1.1, Platform Flash Configuration Register 1
DocID027809 Rev 4
Flash memory controller (PFLASH Controller)
(PFCR1)). Bus masters may be
WAY1
(PFCR1).
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