Table 657. Scr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communications
Offset:
0004h
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1
Only writable when MCR[DRFEN] = 0.
Field
0-14 Reserved
Data Rate Controller mode. Defines the mode setting for LFAST slave device by S/W or LFAST
master.
15 0S/W controls the Data Rate controller mode. In LFAST Slave the ICLC frames for rate change have
no effect on the Data rate.
DRMD
1In LFAST Slave the reception of ICLC frame for rate change sets appropriate speed mode.
In LFAST Master the SCR[DRMD] should be 0.
16 - 22 Reserved
Receiver Data Rate. This bit defines the receiver data rate.
For LFAST Master:
– S/W should program this bit only after transmission of an ICLC frame changing the speed mode of
the slaves Tx interface.
For LFAST Slave:
23 – When SCR[DRMD] = 1, the H/W programs this bit on reception of ICLC frame for changing speed
mode of Slaves Rx interface.
RDR
– The S/W can program this bit when SCR[DRMD] = 0.
– This bit is cleared on MCR[DRFEN] negation.
0Data rate of Rx block is low speed.
1Data rate of Rx block is high speed.
1230/2058
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 642. Speed Control Register (SCR)

Table 657. SCR field descriptions

DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0
RDR
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
0 0 0 0
14 15
0
0 1
30 31
0
TDR
0 0