Pll0 Monitor - STMicroelectronics SPC572L series Reference Manual

Clocking
21.7.1.3 CMU register write protection
The CMU registers have write protection as shown in
by software after being previously locked. A hard lock is only unlocked by a reset once
locked. The REG_PROT module is used to implement the CMU register write protection.
Offset
0000h CMU Control Status Register (CMU_CSR)
0004h CMU Frequency Display Register (CMU_FDR)
0008h CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)
000Ch CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR)
0010h CMU Interrupt Status Register (CMU_ISR)
0014h Reserved
0018h CMU Measurement Duration Register (CMU_MDR)
1. See Register Protection chapter for bit field details.
21.7.2

PLL0 monitor

Software can program an upper and lower limit on the expected PLL0 PHI output clock
frequency. If the monitor is enabled and the measured frequency is above or below the
limits, a flag bit is set and an interrupt, if enabled, is generated. The default condition of the
clock monitor is disabled.
21.7.3 External oscillator (XOSC) monitor
The XOSC frequency is compared to a minimum value limit. If the measured XOSC
frequency is below the limit, a flag is set and an interrupt, if enabled, is generated.
21.7.4 Internal RC oscillator (IRCOSC) monitor
The period of the IRCOSC can be measured in CMU0, using the XOSC as a reference. This
allows for application trimming of the IRCOSC frequency.
476/2058
Table 218. CMU registers availability
Address offset
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
Table 219. CMU register write protection
Register
DocID027809 Rev 4
Register
CMU_CSR
CMU_FDR
CMU_HFREFR
CMU_LFREFR
CMU_ISR
Reserved
CMU_MDR
Table 219. A soft lock can be unlocked
(1)
RM0400
CMU
CMU0
CMU0
CMU0
CMU0
CMU0
—
CMU0
Protections?
Yes
No
No
No
No
No
No