Table 704. Mmfr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
Offset: 040h
0 1 2
R
ST OP
W
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Field
ST Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame.
Operation code.
00 Write frame operation, but not MII compliant.
OP
01 Write frame operation for a valid MII management frame.
10 Read frame operation for a valid MII management frame.
11 Read frame operation, but not MII compliant.
PA PHY address. This field specifies one of up to 32 attached PHY devices.
RA Register address. This field specifies one of up to 32 registers within the specified PHY device.
TA Turn around. This field must be programmed to 10 to generate a valid MII management frame.
DATA Management frame data. This is the field for data to be written to or read from the PHY register.
To perform a read or write operation on the MII Management Interface, write the MMFR. To
generate a valid read or write management frame, ST field must be written with a 01 pattern,
and the TA field must be written with a 10. If other patterns are written to these fields, a
frame is generated, but does not comply with the IEEE 802.3 MII definition.
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a
PHY register), write {01 01 PHYAD REGAD 10 DATA} to the MMFR. Writing this pattern
causes the control logic to shift out the data in the MMFR following a preamble generated by
the control state machine. During this time, contents of the MMFR are altered as the
contents are serially shifted and are unpredictable if read by the user. After the write
management frame operation completes, the MII interrupt is generated. At this time,
contents of the MMFR match the original value written.
To generate an MII management interface read frame (read a PHY register), write {01 10
PHYAD REGAD 10 XXXX} to the MMFR (the content of the DATA field is unimportant).
Writing this pattern causes the control logic to shift out the data in the MMFR register
following a preamble generated by the control state machine. During this time, contents of
the MMFR register are altered as the contents are serially shifted and are unpredictable if
read by the user. After the read management frame operation completes, the MII interrupt is
generated. At this time, the contents of the MMFR register match the original value written
except for the DATA field whose contents are replaced by the value read from the PHY
register.
If the MMFR register is written while frame generation is in progress, the frame contents are
altered. Software must use the MII interrupt to avoid writing to the MMFR while frame
generation is in progress.
1308/2058
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PA
Figure 695. MII Management Frame Register (MMFR)

Table 704. MMFR field descriptions

DocID027809 Rev 4
RA TA
Description
RM0400
Access: User read/write
DATA