Table 821. Slave Node – Rx Mode — Register Setting - STMicroelectronics SPC572L series Reference Manual

LINFlexD
50.3.5.6 Slave node — RX mode
On a slave node in RX mode, the DMA interface requires a DMA RX channel for each ID
filter programmed in RX mode. In case a single DMA RX channel is available, a single ID
field filter must be programmed in RX mode. Each TCD controls a single frame, except for
the extended frames (multiple TCDs). The memory map associated with the TCD chain
(RAM area and LINFlexD registers) is given in
Frame(n)
Master → Slave
Slave → Slave
Extended
Frame(n + 1)
Extended
Frame(n + 2)
The TCD chain of the DMA Rx channel on a slave node supports:
•
Master to Slave: reception of the data field
• Slave to Slave: reception of the data field
The register setting of the LINCR2, IFER, IFMR, and IFCR registers is given in
LIN frame
DDRQ = 0
Master to Slave or
DTRQ = 0
Slave to Slave
HTRQ = 0
The concept FSM to control the DMA Rx interface is given in
moves to Idle state if DMARXE[x] = 0 where x = IFMI – 1. The TCD setting (word transfer) is
given in Table
are allowed.
1448/2058
Figure 837. Slave node — RX memory map
LINFlexD regs
BIDR(4 bytes)
BDRL + BDRM
(4/8 bytes)
BIDR(4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(4/8 bytes)
1 DMA RX channel (TCD single and/or linked chain)
Table 821. Slave node – Rx mode — Register setting
LINCR2 IFER
To enable an ID filter (Rx
mode) for each DMA RX
channel
822. All other TCD fields = 0. TCD settings based on halfword or byte transfer
DocID027809 Rev 4
Figure
RAM area
DMA transfer
BIDR(4 bytes)
BDRL + BDRM
(4/8 bytes)
BIDR(4 bytes)
BDRL + BDRM
(8 bytes)
BDRL + BDRM
(4/8 bytes)
– Identifier list mode
– Identifier mask mode
837.
Linked
IFMR
DFL = payload size
ID = address
CCS = checksum
DIR = 0 (RX)
Figure 838. DMA Rx FSM
RM0400
TCD(n)
TCD(n + 1)
chain
TCD(n + 2)
Table 821.
IFCR