Table 678. Plllsr Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
47.6.2.23 PLL and LVDS Status Register (PLLLSR)
:
Offset 00A4h
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Field
0-27 Reserved
This bit indicates the real time status of the LR sleep signal.
28
0 LR sleep signal is negated.
LRSLPS
1 LR sleep signal is asserted.
This bit indicates the real time status of LD sleep signal.
29
0 LD power sleep signal is negated.
LDSLPS
1 LD power sleep signal is asserted.
This bit indicates the real time status of LD power down signal. When asserted, LD is put in the power
30
down state.
0 LD power down signal is negated.
LDPDS
1 LD power down signal is asserted.
This bit indicates the real time status of LR power down signal. When asserted, LR is put in the power
31
down state.
0 LR power down signal is negated.
LRPDS
1 LR power down signal is asserted.
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 663. PLL and LVDS Status Register (PLLLSR)

Table 678. PLLLSR field descriptions

DocID027809 Rev 4
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0
0 0 0 0
14 15
0 0
1 0
30 31
1 1
1253/2058
1292