Figure 291. Lock0_Pgn Register - STMicroelectronics SPC572L series Reference Manual

RM0400
.
0x0100 LOCK0_PG0
0x0110 LOCK0_PG1
Offset
0x0120 LOCK0_PG2
0x0130 LOCK0_PG3
0 1
R
W
1
Reset x 0
16 17
R
W
1 1
Reset x x
1. If no DCF records have been written to change the lock state, the bit will reset to '1'
Note: The values in the PASS_LOCKxPGn registers override the settings in the flash module's
LOCK0–3 registers.
Values written to the PASS_LOCKxPGn registers do not persist through device reset. The
reset value is determined by DCF record or, if no relevant DCF record has been created,
each mapped bit has a reset value of '1', which causes the associated flash block to be
locked against programming or erase. The purpose of the registers is to indicate secure
write protection status and to provide a way to temporarily override secure write protection.
The PASS_LOCKxPGn bits take effect after the life cycle is matured to "OEM Production" or
older.
Assume four passwords have been created but no DCF records have been written to set the
reset values of the PASS_LOCKx_PGn registers, so the reset value for each mapped bit
defaults to '1', causing all mapped blocks to have four levels of 256-bit password-secured
write protection.
Since the settings in the PASS_LOCKx_PGn registers override the settings in the flash
module's LOCK0–3 registers, the settings in those registers are irrelevant. Each of the four
sets of the PASS module's LOCK registers must be unlocked by supplying the correct
password for each set and then the appropriate bits must be set to '0' to make the desired
flash blocks available for program or erase.
1. First write 0b00 to the PASS_CHSEL[GRP] register field to indicate registers controlled
by password 0 are to be unlocked.
2. Write the 256-bit value for password 0 to the set of eight 32-bit password challenge
input registers (PASS_CINn) beginning with PASS_CIN0. The password must be
written as a sequence of eight 32-bit writes, with the most significant bits of the
password written to PASS CIN0.
3. Write 0xFFCF_FFFF to the PASS_LOCK0_PG0 register and verify a successful write.
4. Repeat the above steps for passwords 1–3.
Just as in previous examples, the result is the following blocks are available for program and
erase operations but at a much higher level of security.
2 3 4 5
1 1 1 1
x x x x
18 19 20 21
1 1 1 1
x x x x

Figure 291. LOCK0_PGn register

Example 15. Overriding secure write protection
Flash Memory Programming and Configuration
6 7 8 9
LOWLOCK
1 1 1
x x x x
22 23 24 25
MIDLOCK
1 1 1
x x x x
DocID027809 Rev 4
10 11 12
1 1 1 1
x x x
26 27 28
1 1 1 1
x x x
Access: Read/Write
13 14 15
1 1 1
x x x
29 30 31
1 1 (1)
x x x
665/2058
673