Functional Description - STMicroelectronics SPC572L series Reference Manual

RM0400
these bits must be protected by periodic CRC or equivalent check implemented at SoC
Level. The following register bits/fields are classified in this category:
•
Section 49.3.2.1: Global Control Register (GBL_CTRL)
•
Section 49.3.2.2: Channel Enable Register (CHNL_EN)
•
Section 49.3.2.4: Fast Message Ready Status Register (FMSG_RDY)
•
Section 49.3.2.5: Slow Serial Message Ready Status Register (SMSG_RDY)
•
Section 49.3.2.6: Data Control Register 1 (DATA_CTRL1)
Control Register 2 (DATA_CTRL2)
• Section 49.3.2.8: Fast Message DMA Control Register (FDMA_CTRL)
•
Section 49.3.2.9: Slow Serial Message DMA Control Register (SDMA_CTRL)
• Section 49.3.2.10: Fast Message Ready Interrupt Control Register (FRDY_IE)
•
Section 49.3.2.11: Slow Serial Message Ready Interrupt Enable Register (SRDY_IE)
• Fast Message DMA Read Register Set and Slow Message DMA Read Register Set
Safety Latent: The register bits/fields in this category should be protected by LBIST at SoC
level. The following register bits/fields are classified in this category:
•
Section 49.3.2.3: Global Status Register (GBL_STATUS)
•
Section 49.3.2.19: Channel 'n' Status Register (n = 0 to (CH-1)) (CHn_STATUS)
•
Section 49.3.2.20: Channel 'n' Configuration Register (n = 0 to (CH-1)) (CHn_CONFIG)
Non-Safety: The following register bits are classified in this category:
•
All other registers and bits fall in this category
49.4

Functional description

49.4.1 Initialization sequence
All the channels are required to be configured before enabling them by writing into
corresponding channel enable bit in the
(CHNL_EN). There are some registers which must be configured and some which are to be
changed if reset value is not as required for that channel. After enabling the channel, no
configuration should be changed and if required to be changed, the user needs to first
disable the channel and then reconfigure the channel parameters. The following must to be
configured before enabling the corresponding channel:
•
Time Stamp Prescaler Value in
to generate the time stamping clock
•
Rx Prescaler Value in
(CH-1)) (CHn_CLK_CTRL)
•
Compensation enable in
to (CH-1)) (CHn_CLK_CTRL)
• Channel Configuration settings in the
Register (n = 0 to (CH-1)) (CHn_CONFIG)
•
Number of Data Nibbles in Channel in the
(DATA_CTRL1)
•
Control bits that control whether messages received in channel are to read by interrupt
or DMA in
Section 49.3.2.9: Slow Serial Message DMA Control Register
Section 49.3.2.1: Global Control Register (GBL_CTRL)
Section 49.3.2.18: Channel 'n' Clock Control Register (n = 0 to
to generate the channel's receiver clock
Section 49.3.2.18: Channel 'n' Clock Control Register (n = 0
and Section 49.3.2.7: Data Control Register 2 (DATA_CTRL2)
Section 49.3.2.8: Fast Message DMA Control Register
DocID027809 Rev 4
Section 49.3.2.2: Channel Enable Register
Section 49.3.2.20: Channel 'n' Configuration
Section 49.3.2.6: Data Control Register 1
SENT Receiver (SRX)
and Section 49.3.2.7: Data
(FDMA_CTRL),
(SDMA_CTRL),
1397/2058
1410