Boundary Scan - STMicroelectronics SPC572L series Reference Manual

RM0400
59.4.4.6 HIGHZ instruction
HIGHZ selects the bypass register as the shift path between TDI and TDO. While HIGHZ is
active all output drivers are placed in an inactive drive state (e.g., high impedance). HIGHZ
also asserts the internal system reset for the MCU to force a predictable internal state.
59.4.4.7 CLAMP instruction
CLAMP allows the state of signals driven from MCU pins to be determined from the
boundary scan register while the bypass register is selected as the serial path between TDI
and TDO. CLAMP enhances test efficiency by reducing the overall shift path to a single bit
(the bypass register) while conducting an EXTEST type of instruction through the boundary
scan register. CLAMP also asserts the internal system reset for the MCU to force a
predictable internal state.
59.4.4.8 ACCESS_AUX_x instructions
The JTAGC is configurable to allow other TAP controllers on the device to share the port
with it. This is done by providing ACCESS_AUX_x instructions for each of these TAP
controllers. When this instruction is loaded, control of the JTAG pins are transferred to the
selected TAP controller. Any data input via TDI and TMS is passed to the selected TAP
controller, and any TDO output from the selected TAP controller is sent back to the JTAGC
to be output on the pins. The JTAGC regains control of the JTAG port during the UPDATE-
DR state if the PAUSE-DR state was entered. Auxiliary TAP controllers are held in RUN-
TEST/IDLE while they are inactive. Instructions not used to access an auxiliary TAP
controller on a device are treated like the BYPASS instruction.
59.4.4.9 BYPASS instruction
BYPASS selects the bypass register, creating a single-bit shift register path between TDI
and TDO. BYPASS enhances test efficiency by reducing the overall shift path when no test
operation of the MCU is required. This allows more rapid movement of test data to and from
other components on a board that are required to perform test functions. While the BYPASS
instruction is active the system logic operates normally.
59.4.5

Boundary scan

The boundary scan technique allows signals at component boundaries to be controlled and
observed through the shift-register stage associated with each pad. Each stage is part of a
larger boundary scan register cell, and cells for each pad are interconnected serially to form
a shift-register chain around the border of the design. The boundary scan register consists
of this shift-register chain, and is connected between TDI and TDO when the EXTEST,
SAMPLE, or SAMPLE/PRELOAD instructions are loaded. The shift-register chain contains
a serial input and serial output, as well as clock and control signals.
59.5 Initialization/Application information
The test logic is a static logic design, and TCK can be stopped in either a high or low state
without loss of data. However, the system clock is not synchronized to TCK internally. Any
mixed operation using both the test logic and the system functional logic requires external
synchronization.
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JTAG Controller (JTAGC)
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