Calculation Of Fifo Pointer Addresses - STMicroelectronics SPC572L series Reference Manual

Deserial Serial Peripheral Interface (DSPI)
46.6.6

Calculation of FIFO pointer addresses

Complete visibility of the TX and CMD and RX FIFO contents is available through the FIFO
registers, and valid entries can be identified through a memory-mapped pointer and a
memory-mapped counter for each FIFO. The pointer to the first-in entry in each FIFO is
memory-mapped.
•
For TX FIFO, the first-in pointer is the Transmit Next Pointer (TXNXTPTR).
•
For CMD FIFO, the first-in pointer is the Command Next Pointer (CMDNXTPTR).
•
For RX FIFO, the first-in pointer is the Pop Next Pointer (POPNXTPTR).
Figure 636
Counter. The TX FIFO is chosen for the illustration, but the concepts are applicable to the
CMD FIFO and RX FIFO.
See Section 46.5.2.4: Transmit First In First Out (TX FIFO) buffering
Section 46.5.2.5: Command First In First Out (CMD FIFO) buffering mechanism
Section 46.5.2.6: Receive First In First Out (RX FIFO) Buffering Mechanism
the FIFO operation.
1218/2058
1
2 20.0 ns
4 40.0 ns
8 80.0 ns
16 160.0 ns
32 320.0 ns
64 640.0 ns
128 1.3 μs
256 2.6 μs
512 5.1 μs
10.2 μs
1024
20.5 μs
2048
41.0 μs
4096
81.9 μs
8192
163.8 μs
16384
327.7 μs
32768
655.4 μs
65536
illustrates the concept of first-in and last-in FIFO entries along with the FIFO
DocID027809 Rev 4
Table 652. Delay values
Delay prescaler values (DSPIn_CTAR[PBR])
3
60.0 ns
120.0 ns
240.0 ns
480.0 ns
960.0 ns
1.9 μs
3.8 μs
7.7 μs
15.4 μs
30.7 μs
61.4 μs
122.9 μs
245.8 μs
491.5 μs
983.0 μs
2.0 ms
RM0400
5 7
100.0 ns 140.0 ns
200.0 ns 280.0 ns
400.0 ns 560.0 ns
1.1 μs
800.0 ns
1.6 μs 2.2 μs
3.2 μs 4.5 μs
6.4 μs 9.0 μs
12.8 μs 17.9 μs
25.6 μs 35.8 μs
51.2 μs 71.7 μs
102.4 μs 143.4 μs
204.8 μs 286.7 μs
409.6 μs 573.4 μs
819.2 μs
1.1 ms
1.6 ms 2.3 ms
3.3 ms 4.6 ms
mechanism,
and
for details on