Standard Features - STMicroelectronics SPC572L series Reference Manual

RM0400
•
Configurable DMA access for each channel
•
CRC protection mechanism
•
Timeout protection mechanism
•
Fixed priority channel selection
•
Data size up to 256 bits on streaming channel
•
Common tag pool for assigning sequential transfer IDs to every new transfer
•
AHB master interface that is used by target node to access shared memory
•
Target node contains a set of nine 32-bit internal registers to store commands
•
Up to two outstanding requests are supported at initiator
45.4.2

Standard features

•
IPS bus interface
• SPP DMA2x bus interface
•
AHB Master Interface
• LFAST Tx/Rx interfaces
•
Cyclic Redundancy Check error detection (CRC16)
45.5 SIPI operation from reset
When the SIPI module exits reset, it is operational and target mode is enabled without the
need to configure the control registers.
45.6 Functional description
45.6.1 External signals
The SIPI has no chip external signals.
45.6.2 Frame format
All frames have the same general format:
•
16 bit header
• Address, Address and Data, or nothing
•
16-bit CRC
There are 2 main groups of command; read and write. Within those 2 groups are three
read/write formats:
•
32-bit
•
16-bit
•
8-bit
DocID027809 Rev 4
Serial Interprocessor Interface (SIPI)
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