External Signal Description - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
48.3

External signal description

Table 696
available modes.
Signal name
FEC_COL X X
FEC_CRS X —
FEC_MDC X —
FEC_MDIO X —
FEC_RXCLK X X
FEC_RXDV X X
FEC_RXD0 X X
FEC_RXD1 X —
FEC_RXD[3:2] X —
FEC_RXER X —
FEC_TXCLK X X
FEC_TXD0 X X
FEC_TXD1 X —
FEC_TXD[3:2] X —
1298/2058
describes the various FEC signals, as well as indicating which signals work in
Table 696. FEC signal descriptions
Asserted upon detection of a collision and remains asserted while the collision
—
persists. This signal is not defined for full-duplex mode.
Carrier sense. When asserted, indicates transmit or receive medium is not idle.
—
In RMII mode, this signal is present on the FEC_RXDV pin.
Output clock provides a timing reference to the PHY for data transfers on the
X
FEC_MDIO signal.
Transfers control information between the external PHY and the media-access
controller. Data is synchronous to FEC_MDC. This signal is an input after reset.
X
When the FEC operates in 10Mbps 7-wire interface mode, this signal should be
connected to VSS.
— Provides a timing reference for FEC_RXDV, FEC_RXD[3:0], and FEC_RXER.
Asserting the FEC_RXDV input indicates PHY has valid nibbles present on the MII.
FEC_RXDV must remain asserted from the first recovered nibble of the frame
through to the last nibble. Assertion of FEC_RXDV must start no later than the SFD
X
and exclude any EOF.
In RMII mode, this pin also generates the CRS signal.
This pin contains the Ethernet input data transferred from PHY to the media-access
X
controller when FEC_RXDV is asserted.
This pin contains the Ethernet input data transferred from PHY to the media access
X
controller when FEC_RXDV is asserted.
These pins contain the Ethernet input data transferred from PHY to the media
—
access controller when FEC_RXDV is asserted.
When asserted with FEC_RXDV, indicates PHY detects an error in the current
X
frame. When FEC_RXDV is not asserted, FEC_RXER has no effect.
Input clock which provides a timing reference for FEC_TXEN, FEC_TXD[3:0] and
FEC_TXER.
X
In RMII mode, this signal is the reference clock for receive, transmit, and the
control interface.
X The serial output Ethernet data and only valid during the assertion of FEC_TXEN.
This pin contains the serial output Ethernet data and valid only during assertion of
X
FEC_TXEN.
These pins contain the serial output Ethernet data and valid only during assertion
—
of FEC_TXEN.
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Description
RM0400