Table 1007. Jtagm_Mcr Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

JTAG Master (JTAGM)
Offset: 0x00
0 1
R
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
The JTAGM_MCR register is described in
Field
0
SWRESET
1–2
EVTO0_SENSE
3–4
EVTO1_SENSE
5
EVTO_IE
6
EVTI0_ASSERT
1808/2058
2 3 4 5
0 0 0 0
18 19 20 21
INTER_JTAG_FRAME_TIMER
0 0 0 0
Figure 1054. JTAGM_MCR register

Table 1007. JTAGM_MCR register field descriptions

Software Reset.
Writing a 1 resets the state machine and counters inside JTAGM.
It is a self clearing bit. Writing a 0 has no effect.
Note: After being written to "1", this bit is auto cleared within 3 TCK cycles.
Determines JTAGM response to activity on EVTO0
00 No action is taken by the JTAGM in response to any EVTO0 edges (default setting)
01 EVTO0_EDGE status bit is set whenever a falling edge is detected on EVTO0
10 EVTO0_EDGE status bit is set whenever a rising edge is detected on EVTO0
11 EVTO0_EDGE status bit is set whenever a falling or rising edge is detected on EVTO0
Determines JTAGM response to activity on EVTO1 line
00 No action is taken by the JTAGM in response to any EVTO1 edges (default setting)
01 EVTO1_EDGE status bit is set whenever a falling edge is detected on EVTO1
10 EVTO1_EDGE status bit is set whenever a rising edge is detected on EVTO1
11 EVTO1_EDGE status bit is set whenever a falling or rising edge is detected on EVTO1
Enables EVTO triggered JTAGM interrupt
0 No JTAGM interrupt is generated In response to any EVTO0 or EVTO1 activity
1 JTAGM interrupt is generated when EVTO0_EDGE or EVTO1_EDGE are set
EVTI0 Assert.
0 Asserted the EVTO0 from the JTAGM module
1 Deasserts the EVTO0 from the JTAGM module
DocID027809 Rev 4
6 7 8 9
0 0
1 1 0 0
22 23 24 25
0
SIE
0 0 0 0
Table 1007.
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
IIE TCKSEL
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
DTM
1 0