Modes Of Operation - STMicroelectronics SPC572L series Reference Manual

RM0400
49.1.2

Modes of operation

49.1.2.1 Debug mode
In debug mode, message reception will be halted and all existing status and messages will
be retained. DBG_FRZ bit is required to be set for this mode. On debug exit, a calibration
length error (CAL_LEN_ERR) can be reported and the channels will start receiving
messages from a valid calibration pulse.
49.1.2.2 Low power modes
SENT Receiver behavior is affected by chip-specific low power modes (for example, STOP
or WAIT modes). These low power modes should either gate-off both the system bus clock
and the protocol clocks or reduce their frequencies, depending on the application.
On exiting from these low power modes, calibration length error (CAL_LEN_ERR) can get
set in channel status registers as the SENT sensor (transmitter) could be in the middle of a
message transmission at that point. Thus, software should clear all error status bits after
exiting the low power modes.
Modes where both system bus clock and protocol clock are gated: In this case, both
message reception and interrupt / DMA request generation will halt. The internal receiver
channels will freeze (since clock is not there) and will not receive any messages. Messages
which are completely received before entering the low power mode can be read after the
low power mode exit.
Modes where frequency of system bus clock is changed: For reduced power
consumption the system bus clock can be reduced but not below a minimum value (See
Section 49.5.2: System bus clock requirements on page
messages. Protocol clock should not go below the minimum value (See
High frequency receiver clock (protocol clock) requirements on page
receive operations.
Note: Gating of clocks in the low power mode is chip-specific, see the chapter that refers how the
modules behave in low power modes.
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SENT Receiver (SRX)
1409) to avoid overflow of received
Section 49.5.3:
1410) for accurate
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