Fetch Trace - STMicroelectronics SPC572L series Reference Manual

RM0400
1. Since all addresses are considered to be out of range, a Data Trace Event may be recognized if the DTC register is
programmed so that addresses out of range are queued.
Note: Before sending through the NAR interface, the MCS, DPLL or ARU Data Trace message is
buffered. Due to bandwidth constraints in the NAR interface and in the data trace buffering,
this data trace message can be lost when superseded by another data trace message from
the same source. In this case an error message is sent. See
about GTMDI NAR messages.
42.6.8.4 DPLL data trace
DPLL Data Trace is a straight forward implementation in which the trace is enabled using
the DMC bit in the
RAM1a, RAM1b or RAM2 for tracing using the RAMSEL bit in the same register. Only one
memory module is selected for tracing at a given time. Start/Stop inputs from the SPU
module can be used to control the DPLL Data Trace messages as well as JTAG interface.
This is achieved by controlling the DMC bit which can be done from SPU or JTAG interface.
See Table 477
42.6.8.5 ARU data trace
The GTM module selects two ARU addresses to be monitored, using the ARU Debugging
Channels 0 and 1, see the GTM documentation for details on how to program these
channels. The data trace for these two channels is controlled by DMC1/2 bits in the
GTMDI_ARU_DTC, see
(GTMDI_ARU_DTC). Once enabled, messages are generated as soon as a valid data is
identified in one of the ARU Debugging Channels, 0 or 1.
42.6.9

Fetch trace

Fetch trace tries to record all instruction fetch accesses done by an MCS channel. Fetch
trace is handled independently for each MCS channel, therefore what happens to a certain
channel does not affect other channels since all channels run independently. Even error
conditions are handled independently for each channel.
Fetch trace can be enabled/disabled by two ways:
•
By watchpoint hit, if the watchpoint is configured to do so
•
Directly by register
When a fetch access hits a watchpoint and the last enables fetch trace (having it disabled
before the watchpoint hit), that access is ignored by the fetch trace logic.
42.6.9.1 Enabling MCS program fetch trace
Program fetch trace for the MCS is enabled on a channel by channel basis. This selective
enabling allows the debug tool to control the bandwidth for the transmitted messages. The
program fetch trace is enabled through a JTAG register, see
Figure 463. Data trace address range options
Programmed Value
DTSA =< DTEA
DTSA > DTEA
Figure 424. It is possible to select individual DPLL RAM modules such as
for more details about the bits that should be used in this process.
Section 42.5.1.26, ARU data trace control register
DocID027809 Rev 4
GTM Development Interface (GTMDI)
Range Selected
[DTSA: DTEA]
All addresses are out of range
Table 505
Figure
(1)
for more details
434.Since the registers
957/2058
960