Interprocessor Communications - STMicroelectronics SPC572L series Reference Manual

RM0400 LVDS Fast Asynchronous Serial Transmission (LFAST) – Interprocessor Communica-
47 LVDS Fast Asynchronous Serial Transmission
(LFAST) – Interprocessor Communications
47.1 Introduction
This chapter describes the specifications of the LVDS Fast Asynchronous Serial
Transmission (LFAST) module. LFAST is used in dual mode (software configurable
master/slave operation) for interprocessor communications.
47.2 Block diagram
Figure 637
SIPI
Signal Status
Test & Debug
Interface
47.3 External signals
LFAST is a five pin interface with the following signals:
•
lfast_sysclk
–
•
txdatap/txdatan
–
•
rxdatap/rxdatan
–
depicts LFAST interaction with other modules on the device.
Figure 637. LFAST block diagram
Samplers
System
Side Module
Interface
Reference clock of the LFAST master and slave
Differential transmit (Tx) interface pair
Differential receive (Rx) interface pair
DocID027809 Rev 4
Clock Control
Module
LFAST Core
Module
IPS Interface
lfast_sysclk
Tx LVDS
LD
Interface
Rx LVDS
LR
Interface
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