STMicroelectronics SPC572L series Reference Manual page 971

RM0400
Offset
0x01018+n*0x80 +
Channel n TDU control (TIM[i]_CH[n]_TDUV)
BBi
0x0101C+n*0x80 + Channel n filter parameter 0
BBi (TIM[i]_CH[n]_FLT_RE)
0x01020+n*0x80 + Channel n filter parameter 1
BBi (TIM[i]_CH[n]_FLT_FE)
0x01024+n*0x80 +
Channel n control (TIM[i]_CH[n]_CTRL)
BBi
0x01028+n*0x80 +
Channel n control (TIM[i]_CH[n]_ECTRL)
BBi
0x0102C+n*0x80 + Channel n interrupt notification
BBi (TIM[i]_CH[n]_IRQ_NOTIFY)
0x01030+n*0x80 + Channel n interrupt enable
BBi (TIM[i]_CH[n]_IRQ_EN)
0x01034+n*0x80 + Channel n software interrupt force
BBi (TIM[i]_CH[n]_IRQ_FORCINT)
0x01038+n*0x80 + Channel n IRQ mode configuration register
BBi (TIM[i]_CH[n]_IRQ_MODE)
0x0103C+n*0x80 + Channel n software interrupt force
BBi (TIM[i]_CH[n]_EIRQ_EN)
(0x01040+n*0x80 –
0x01074+n*0x80) +
BBi
Channel n IRQ mode configuration register
0x01078 + BBi
(TIM[i]_IN_SRC)
0x107C + BBi TIM Global software reset (TIM[i]_RST)
(0x01078+n*0x80 –
0x0107C+n*0x80) +
BBi
(0x01400 –
0x017FC) + BBi
0x02000 – 0x04400
0x04404 – 0x07FFC
0x08000 + n*0x0040 TOM Channel m control register
+ CCi (TOM[i]_CH[n]_CTRL), i = 0...1, n = 0...15
0x08004 + n*0x0040 TOM Channel n CCU0 compare shadow
+ CCi register (TOM[i]_CH[n]_SR0)
0x08008 + n*0x0040 TOM Channel n CCU1 compare shadow
+ CCi register (TOM[i]_CH[n]_SR1)
Table 516. GTMINT module memory map(Continued)
Use
Timer Output Module (TOM) Configuration Registers
(CCi = i*0x800, i = 0...1, n = 0...15)
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved for TIM[i]_CH[n]
R/W
R/W
Reserved (n > 0)
Reserved
Reserved for TIM2 to TIM6
Reserved
R/W
R/W
R/W
(1)
Reset value Location
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_X000 See GTM Spec.
0x0000_0000 See GTM Spec.
0x0000_0000 See GTM Spec.
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
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