STMicroelectronics SPC572L series Reference Manual page 965

RM0400
Offset
0x00000300
0x00000600
0x00000800
0x00000880
0x00000F00
0x00000F40
0x00001000
0x00001800
0x00008000
0x00008800
0x0000D000
0x0000D800
0x0000E000
0x00018000
0x00018080
0x00018400
0x00019000
0x00028000
0x00028200
0x00028400
0x00028600
0x00028E00
0x0002C000
0x00030000
0x00031000
0x00038000
0x00040000
1. Configuration of GTM has to be confirmed for final silicon
This section presents the GTMINT Module Memory Map (that is basically the same of the
timer GTM-IP) in
Table 515. High level memory map(Continued)
Table 516.
DocID027809 Rev 4
GTM101 Integration (GTMINT) Module
(1)
Use
CMU
ICM
SPE0
SPE1
MAP
MCFG
TIM0
TIM1
TOM0
TOM1
ATOM0
ATOM1
ATOM2
F2A0
AFD0
FIFO0
FIFO0_MEMORY
DPLL
DPLL_MEM R1A
DPLL_MEM R1B
DPLL_MEM_REGION R1C
DPLL REGION EXT
DPLL_MEM R2
MCS0
MCS1
MCS0_MEMORY
MCS1_MEMORY
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