Destructive' Resets - STMicroelectronics SPC572L series Reference Manual

RM0400
51.4.2

'Destructive' resets

A 'destructive' reset indicates that an event has occurred after which critical register or
memory content can no longer be guaranteed. Exceptions to the latter are the software
'destructive' reset and the external power-on reset which do allow the memory content to be
preserved if the chip is configured to not execute a self test on power-on, 'destructive', and
external resets.
The status flag associated with a given 'destructive' reset event
(RGM_DES.F_<destructive reset> bit) is set when the 'destructive' reset is asserted and the
power-on reset is not asserted. It is possible for multiple status bits to be set simultaneously,
and it is software's responsibility to determine which reset source is the most critical for the
application.
A given 'destructive' reset can be optionally disabled by writing bit
RGM_DERD.D_<destructive reset>
Note: The RGM_DERD register can be written only once between two 'destructive' reset events.
The chip's low-voltage detector threshold ensures that, when 'destructive' voltage out of
range (LVD and/or HVD) is enabled, the supply is sufficient to have the 'destructive' event
correctly propagated through the digital logic. Therefore, if a given 'destructive' reset is
enabled, the MC_RGM ensures that the associated reset event is correctly triggered to the
full system. However, if the given 'destructive' reset is disabled and the voltage goes below
the digital functional threshold, functionality can no longer be ensured, and the reset may or
may not be asserted.
An enabled 'destructive' reset triggers a reset sequence starting from the beginning of
PHASE0.
51.4.2.1 External power-on reset—PORST
The bidirectional external power-on reset pin PORST is a special case 'destructive' reset.
The detection of a falling edge on PORST starts the reset sequence.RGM_PHASE1
The chip asserts PORST if the reset sequence was triggered by one of the following:
•
a power-on reset
•
a 'destructive' reset event
In this case, PORST is asserted until the end of PHASE0.
The PORST input is disabled immediately as of the PORST output being asserted in order
to prevent a falling edge from being detected while the pin is being driven from the chip. The
input is then re-enabled 4 ms after the PORST output stops being driven by the chip in order
to allow the pull-up on the pin to take effect.
In addition, the reset sequence is not exited into application until PORST is no longer driven
low from off-chip. In the case the chip is configured to execute a self test on power-on,
'destructive', and external resets, this is the exit of PHASE3 after self test execution has
completed.
51.4.3 External reset
The MC_RGM manages the external reset coming from ESR0. The detection of a falling
edge on ESR0 starts the reset sequence.
DocID027809 Rev 4
Reset Generation Module (MC_RGM)
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