Gtm Integration Module Configuration; Communication Interfaces; Fec Interface - STMicroelectronics SPC572L series Reference Manual

RM0400
Absolute address (hex)
FFF8_0000
FFF8_00E0 –
FFF8_00E4
FFF8_00F0 –
FFF8_00FC
FFF8_0100 – FFF8_017C
FFF8_0180 – FFF8_3FFF Reserved
1. The reset value of PIT1_MCR is 0x02.
Absolute address (hex)
FFF8_4000
FFF8_40E0
FFF8_40E4
FFF8_40F0 – FFF8_40F8 Reserved
FFF8_4100 – FFF8_411C
FFF8_4120 – FFF8_7FFF Reserved
1. The reset value of PIT0_MCR is 0x06.
6.6.2.4 PIT clocking
The PIT0 standard channels are clocked with the peripheral clock (PER_CLK). The PIT 1
channels are clocked with the peripheral clock (PER_CLK).
6.6.3

GTM integration module configuration

The GTM101 integration module (GTMINT) is an interface to the General Timer Module 101
that adds ECC functionality and a Nexus-based system debugger interface (GTMDI). It has
two control registers and provides access to the GTM101's memory-mapped registers. The
GTM101 is detailed separately in the GTM-IP_101_Specifcation. See
Integration (GTMINT) Module
6.7

Communication interfaces

6.7.1

FEC interface

The Fast Ethernet Controller on the SPC572Lx device only supports the Reduced Media
Independant Interface (RMII) mode. The MII_MODE field in the Receive Control Register
Figure 698: Receive Control Register (RCR)
initialization — see
Table 40. PIT1 memory map
PIT Module Control Register (PIT1_MCR)
Reserved
Reserved
Timer Channel [0:3] Registers (PIT1_LDVALn, PIT1_CVALn, PIT1_TCTRLn, and
PIT1_TFLGn)
Table 41. PIT0 memory map
PIT Module Control Register (PIT0_MCR)
PIT Upper Lifetime Timer Register (PIT0_LTMR64H)
PIT Lower Lifetime Timer Register (PIT0_LTMR64L)
Timer Channel [0:1] Registers (PIT0_LDVALn, PIT0_CVALn, PIT0_TCTRLn, and
PIT0_TFLGn)
for more information.
Section 48.5.7: User initialization (after setting
DocID027809 Rev 4
Register name
(1)
Register name
(1)
must be set by the user to '1' prior to FEC
ECR[ETHER_EN]).
Device configuration
Chapter 43: GTM101
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