Tap.7 Architecture - STMicroelectronics SPC572L series Reference Manual

IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
The notation used in the table is as follows:
•
M = Mandatory signal
•
MC = Mandatory signal with expanded functionality
•
O = Optional signal
•
OC = Optional signal with expanded functionality
The CJTAG module provides T4 capability and implements the TCKC, TMSC, TDIC, TDOC,
and nTRST pins.
Signal Name
TCK/TCKC
TMS/TMSC
TDI/TDIC
TDO/TDOC
nTRST
Mandatory signal count (minimum)
60.3.4

TAP.7 architecture

The TAP.7 hardware architecture is shown in
layers listed below:
•
STL – System Test Logic – Logic with 1149.1 compliant behavior and underlying TAP
hierarchy (T0 capabilities). Provides an IEEE 1149.1 interface for the T0 TAP.7. This
logic is outside the CJTAG module.
•
RSU – Reset and Selection Unit – A hardware layer that is placed between the APU,
EPU, or STL and the TAP.7 signals (Added as an option to support the use of the
Control Protocol) Provides reset and TAP.7 Controller selection services.
•
EPU – Extended Protocol Unit – A hardware layer that is placed between the STL
and the TAP.7 signals. (Added for T1, T2, and T3 capabilities). Provides an IEEE
1149.1 interface for the T1–T3 TAP.7s.
•
APU – Advanced Protocol Unit – A hardware layer that is placed between the
STL/EPU and the TAP.7 signals (added for T4 capabilities). Provides a T4 TAP.7
interface that is either narrow or wide, with the wide version providing an IEEE 1149.1
interface.
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Table 972. TAP.7 signal list
Description
Test clock
Test mode select
Test data input
Test data output
Test reset
DocID027809 Rev 4
T4 T3
MC M
MC M
OC MC
OC MC
O O
2 4
Figure 1026. It is described with the hardware
RM0400
Class
T2 T1 T0
M M M
M M M
M M M
M M M
O O O
4 4 4