Table 103. External Input Interrupt—Register Settings - STMicroelectronics SPC572L series Reference Manual

RM0400
Register
Set to the effective address of the instruction that the processor would have attempted to execute next
SRR0
if no exception conditions were present.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
ESR Unchanged
MCSR Unchanged
DEAR Unchanged
IVPR || 0x40 (autovectored)
0:23
Vector
IVPR0:15 || (IVPR16:29 | p_voffset[0:13]) || 2'b00 (non-autovectored)
12.6.5.6 Alignment Interrupt (offset 0x50)
An Alignment exception is generated when any of the following occurs:
• The operand of lmw or stmw is not word aligned.
•
The operand of lwarx or stwcx. is not word aligned.
• The operand of lharx or sthcx. is not halfword aligned.
•
Execution of a dcbz instruction is attempted.
Table 104
Register
SRR0 Set to the effective address of the excepting load/store/dcbz instruction.
SRR1 Set to the contents of the MSR at the time of the interrupt
SPV 0
WE 0
MSR CE —
EE 0
PR 0
ESR [ST], VLEMI. All other bits cleared.
MCSR Unchanged
DEAR Set to the effective address of a byte of the load or store access causing the violation.
Vector IVPR || 0x50
0:23
Table 103. External Input Interrupt—register settings
FP
ME
FE0
DE
lists register settings when an alignment interrupt is taken.
Table 104. Alignment Interrupt—register settings
FP
ME
FE0
DE
DocID027809 Rev 4
Setting description
0
—
0
—
Setting description
0
—
0
—
Core e200z215An3 description
FE1 0
IS 0
DS 0
PMM 0
RI —
FE1 0
IS 0
DS 0
PMM 0
RI —
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