Table 630. Dspi_Ssr0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
When DSICR1[DSI64E] is set, SSR1 is the MSB half and SSR0 is the LSB half of the 64-bit
SSR.
Address: Base + 0x00D4
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 601. DSPI DSI Serialization Source Select Register 0 (DSPI_SSR0)
Field
Source Select
Select the serialization source for the 32 LSB of DSI frame.
0–31
Each SS bit selects data for a corresponded bit in the transmitted frame.
SS
0The bit in the transmitted frame is taken from the parallel input pin.
1The bit in the transmitted frame is taken from the ASDR0 register
46.3.19 DSPI DSI Deserialized Data Interrupt Mask Register 0 (DSPI_DIMR0)
DIMR0 selects bits in the 32 LSB of received DSI frame to be checked to generate the DDI
interrupt.
When DSICR1[DSI64E] is set, DIMR1 is the MSB half and DIMR0 is the LSB half of the 64-
bit DIMR.
Address: Base + 0x00E8
0 1
R
W
Reset 0 0
16 17
R
W
Reset 0 0
Figure 602. DSPI DSI Deserialized Data Interrupt Mask Register 0 (DSPI_DIMR0)
2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0

Table 630. DSPI_SSR0 field descriptions

2 3 4 5
0 0 0 0
18 19 20 21
0 0 0 0
DocID027809 Rev 4
Deserial Serial Peripheral Interface (DSPI)
6 7 8 9
SS
0 0 0 0
22 23 24 25
SS
0 0 0 0
Description
6 7 8 9
MASK
0 0 0 0
22 23 24 25
MASK
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
26 27 28 29
0 0 0 0
14 15
0 0
30 31
0 0
14 15
0 0
30 31
0 0
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