Table 846. Ifcr2N+1 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

LINFlexD
Field
Reserved
0–15
Read returns a 0
Data Field Length
16–21
Number of data bytes in the response part of the frame.
DFL[5:0]
DFL[5:0] = Number of data bytes – 1
Direction
22
This bit controls the direction of the data field.
DIR
0 LINFlexD receives data and copies to the BDR registers
1 LINFlexD transmits data from the BDR registers
Classic Checksum
This bit controls the type of checksum applied on the current message.
23
0 Enhanced Checksum covering Identifier and Data fields
CCS
This is compatible with LIN specification rev. 2.0 and higher.
1 Classic Checksum covering Data field only
This is compatible with LIN specification 1.3 and lower.
Reserved
24–25
Forced to 0 by hardware.
26–31 Identifier
ID[5:0] Identifier part of the identifier field without the identifier parity.
50.4.2.22 Global Control Register (GCR)
This register is read-only in Normal mode and can be programmed only in Initialization
mode. This is a global control register — in other words, the register configuration will be
applied in LIN mode as well as in UART mode.
4C+4×no_of_filters×slave
Address:
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
1
This field can be read in any modes and written only in Initialization mode.
2
This field can be written only by software in Initialization mode. This field reads 0 by software.
3
Refer to device configuration chapter to see the number of filters and value of slave used in the device.
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Table 846. IFCR2n+1 field descriptions

3
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0 0
0 0 0 0
Figure 866. Global Control Register (GCR)
DocID027809 Rev 4
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0 0 0 0
RM0400
14 15
0 0
0 0
30 31
2
SR
0 0