Inter-Packet Gap (Ipg) Time - STMicroelectronics SPC572L series Reference Manual

Fast Ethernet Controller (FEC)
48.5.14

Inter-Packet Gap (IPG) time

The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After
completing a transmission or after the backoff algorithm completes, the transmitter waits for
carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission
may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit
times. If carrier sense asserts during the last 36 bit times, it is ignored and a collision occurs.
The receiver accepts back-to-back frames with a minimum spacing of at least 28 bit times. If
an inter-packet gap between receive frames is less than 28 bit times, the receiver may
discard the following frame.
48.5.15 Collision managing
If a collision occurs during frame transmission, the Ethernet controller continues the
transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the
collision occurs during the sequence, a JAM pattern is sent after the end of the preamble
sequence.
If a collision occurs within 512 bit times (one slot time), the retry process is initiated. The
transmitter waits a random number of slot times. If a collision occurs after 512 bit times, then
no retransmission is performed and the end of frame buffer is closed with a Late Collision
(LC) error indication.
48.5.16 MII internal and external loopback
Internal and external loopback are supported by the Ethernet controller. In loopback mode,
both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Internal
and external loopback are configured using combinations of the RCR[LOOP, DRT] and
TCR[FDEN] bits.
Set FDEN for internal and external loopback.
For internal loopback, set RCR[LOOP] and clear RCR[DRT]. FEC_TXEN and FEC_TXER
do not assert during internal loopback. During internal loopback, the transmit/receive data
rate is higher than in normal operation because the transmit and receive blocks use the
internal bus clock instead of the clocks from the external transceiver. This causes an
increase in the required system bus bandwidth for transmit and receive data being DMA'd
to/from external memory. It may be necessary to pace the frames on the transmit side
and/or limit the size of the frames to prevent transmit FIFO underruns and receive FIFO
overflows.
For external loopback, clear RCR[LOOP] and RCR[DRT], and configure the external
transceiver for loopback.
48.5.17 RMII loopback
The FEC also supports RMII loopback. In this mode, transmit data is sent to the RMII
receive logic and out the FEC_TXD[1:0] pins. To enable RMII loopback mode, set
RCR[RMII_MODE, RMII_LOOP] and TCR[FDEN] and clear RCR[RMII_ECHO, LOOP].
1356/2058 DocID027809 Rev 4
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