Table 117. Siul2_Direr0 Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
27 Reserved
28–31
External Interrupt Status Flag x—This flag can be cleared only by writing 1. Writing 0 has no
EIF3
effect. If enabled (SIUL2_DIRER[x]), EIF[x] causes an interrupt or DMA request.
EIF2
0 No interrupt or DMA event has occurred on the pad
EIF1
1 An interrupt or DMA event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
EIF0
13.2.2.4 SIUL2 DMA/Interrupt Request Enable Register 0 (SIUL2_DIRER0)
The DMA/Interrupt Request Enable Register enables the assertion of DMA or interrupt
request if the corresponding External IRQ Flag bit is set in SIUL2 DMA/Interrupt Status Flag
Register0 (SIUL2_DISR0). The type of request enabled is determined by the corresponding
DMA/Interrupt Request Select bit in SIUL2 DMA/Interrupt Request Select Register0
(SIUL2_DIRSR0). This register enables the interrupt messaging to the interrupt controller.
Address: 0x0018
0 1
R 0 0
W
Reset 0 0
16 17
R 0 0
W
Reset 0 0
Figure 57. SIUL2 DMA/Interrupt Request Enable Register 0 (SIUL2_DIRER0)
Field
0–20 Reserved
External Interrupt or DMA Request Enable x
21
0 Interrupt or DMA requests from the corresponding EIF[x] bit are disabled
EIRE10
1 Set EIF[x] bit causes either a DMA or an interrupt request depending on SIUL2_DIRSR
22–25 Reserved
External Interrupt or DMA Request Enable x
26
0 Interrupt or DMA requests from the corresponding EIF[x] bit are disabled
EIRE5
1 Set EIF[x] bit causes either a DMA or an interrupt request depending on SIUL2_DIRSR
Table 116. SIUL2_DISR0 field descriptions(Continued)
2 3 4 5
0 0 0 0
0 0 0 0
18 19 20 21
0 0 0
EIRE
10
0 0 0 0

Table 117. SIUL2_DIRER0 field descriptions

DocID027809 Rev 4
System Integration Unit Lite2 (SIUL2)
Description
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
0 0 0 0
0 0 0 0
Description
Access: User read/write
10 11 12 13
0 0 0 0
0 0 0 0
26 27 28 29
0
EIRE EIRE EIRE
5 3 2
0 0 0 0
14 15
0 0
0 0
30 31
EIRE EIRE
1 0
0 0
291/2058
308