Figure 793. Dma Slow Serial Message Bit2 Read Register (Dma_Smsg_Bit2) - STMicroelectronics SPC572L series Reference Manual

SENT Receiver (SRX)
Table 804. DMA_SMSG_BIT3 Field Descriptions(Continued)
Field
7:30
ID or Data Field. Value depends on setting of 'C' bit. If 'C' bit is 0, this field is ID[3:0] and if the 'C' bit
ID[3:0]/DATA
is 1, this field is Data[15:12]
[15:12]
31 0 as per SAE Specification
Note: If the TYPE bit in the register reads '0', then remainder bits (for CFG, ID & DATA) will be
redundant and read zeros. The short serial message will be located in DMA_SMSG_BIT2
register fields. If TYPE bit is '1', then the message in register is Enhanced Serial Message
and using CFG bit, software can decode the ID & DATA fields.
49.3.2.16 DMA Slow Serial Message Bit2 Read Register (DMA_SMSG_BIT2)
This register (DMA_SMSG_BIT2) is common for all types of slow serial messages. Hence,
the register fields have been placed in such a way to match the bit positions in actual
message defined by SAE Specification as shown in
Figure 800
reading this register for these two types of messages.
message.
DMA Source Size must be set to 32 bits when reading this register via DMA.
Address Offset: 0x0054
0
R
W
Reset 0
8
R
W
Reset 0
16
R
W
Reset 0
24
R
W
Reset 0

Figure 793. DMA Slow Serial Message Bit2 Read Register (DMA_SMSG_BIT2)

1386/2058
and Figure 801 shows the enhanced serial messages format to be used when
1 2
0 0
9 10
0 0
17 18
0 0
25 26
0 0
DocID027809 Rev 4
Description
Figure
Figure 802
3 4
0 0
11 12
SMCRC
0 0
19 20
0 0
27 28
DATA[7:0]
0 0
800, Figure 801 and Figure
shows the short serial
5 6
0 0
13 14
0 0
21 22
DATA[11:8]
0 0
29 30
0 0
RM0400
802.
Access: R
7
0
15
0
23
0
31
0