Table 578. Tx Core Release Register Field Descriptions - STMicroelectronics SPC572L series Reference Manual

RM0400
Field
0:3 Core Release
REL One digit, BCD-coded.
4:7 Step of Core Release
STEP One digit, BCD-coded.
8:11 Sub-step of Core Release
SUBSTEP One digit, BCD-coded.
12:15 Time Stamp Year
YEAR One digit, BCD-coded.
12:15 Time Stamp Month
MON Two digits, BCD-coded.
12:15 Time Stamp Day
DAY Two digits, BCD-coded.
Release Step
1 0
44.3.16.3.3 Calibration Configuration Register (CCFG)
Address: 0x1
0 1 2
R 0 0
SWR
W
Reset 0 0 0
16 17 18
R
W
Reset 0 0 0
1. Write access by the Host CPU to registers/bits marked with "P=Protected Write" is possible only when input cu_cce = '1'.
Signal cu_cce is activated when the M_CAN control bits CCCR.CCE = '1' AND CCCR.INIT = '1'.

Table 578. Tx Core Release Register field descriptions

Table 579. Example for Coding of Revisions
SubStep Year
0 2
3 4 5
0 0 0
0 0 0
19 20 21
1
OCPM
0 0 1
Figure 533. Calibration Configuration Register (CCFG)
DocID027809 Rev 4
Description
Month
02
6 7 8 9
0 0 0 0
0 0 0 0
22 23 24 25
BCC
1
CFL
1
0 0 0 0
CAN Subsystem
Day Name
Revision 1.0.0, Date
20
2012/02/20
10 11 12 13
0 0
CDIV
0 0 0 0
26 27 28 29
0
TQBT
0 0 0 1
Access: RP
14 15
(1)
0 0
30 31
1
0 0
1077/2058
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