Figure 218. Mc_Cgm System Clock Ramp-Down Timing (K = 6 Example) - STMicroelectronics SPC572L series Reference Manual

Clock Generation Module (MC_CGM)

Figure 218. MC_CGM System Clock Ramp-Down Timing (k = 6 example)

f
f
curr
16MHz
24.4.1.2.6 Clock Ramp-Up
The clock ramp-up starts with the given divider value PCS_DIVSn[DIVS] and with the given divider
decrement value PCD_DIVCn[INIT] and ends with the divider value 1.
The initial divider change start value PCS_DIVCn[INIT] for system clock ramp-up is given in
Equation 11
Where k is calculated from
start value for clock ramp-up is given in
Equation 12
532/2058
CGM_PCS_SDUR
1 2
PCS_DIVCn[INIT]
Equation 9 using the target system clock source frequency f
Equation 12
PCS_DIVSn[DIVS]
DocID027809 Rev 4
3 4
busy
× ×
= d k 1000 1 –
.
( )
k k + 1
 
-------------------- ×
= 1 + d 1000
 
2
≤ a × f
curr
÷ PCS_DIVEn[DIVE]
f
curr
steps
5 6
Equation 11
. The divider
targ
– 1
RM0400
.